1-trit Ternary Multiplier and Adder Designs Using Ternary Multiplexers and Unary Operators

Abstract

This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs (Ternary Multiplexers) and unary operators. The target of the proposed designs is to minimize energy consumption in nanoscale embedded circuits to improve their battery usage. To achieve that, different techniques are used: 32-nm CNTFET tranisistor, Multiple-Valued Logic (MVL), two voltage supplies $(V_{dd},\ V_{dd}/2)$ TMUXs, and unary operators to reduce the transistors' number and PDP (Power Delay Product). Extensive simulations using HSPICE for different Process, Voltage, Temperature (PVT), and noise effects are applied. The obtained results show improvements regarding PDP, robustness of process variations, and noise tolerance with respect to recent similar designs.