Deep Submicron USLI Design Paradigm: Who is Writing the Future?

K. Eshraghian
{"title":"Deep Submicron USLI Design Paradigm: Who is Writing the Future?","authors":"K. Eshraghian","doi":"10.1109/ISQED.2000.10014","DOIUrl":null,"url":null,"abstract":"The concept of \"technology generation\" attributed to Gordon Moore has created a plausible method for predicting the behavior of technology road map that has seen world's production of silicon CMOS to exceed 75% of electronic related materials. A feature of such progress is characterized by the complexity factor that predicts the emergence of a new generation of technology every three years.A reasonable method of comparison would be to observe the parallel between CMOS based systems with those of biologically inspired systems. Deep submicron, synonymous with Ultra Large Scale of integration, suggests that by the year 2010 the number of transistors/chip will be in the order of 0.5x10 9 , with an intrinsic clock speed of 3GHz. At this level of integration the classic MOS transistor would have only a few ?electrons' in the channel to direct. Thus, the reality of Quantum MOS (QMOS) transistor becomes a plausible possibility.In the mean time the question remains as to how are we going to cope with the design and quality of the new system complexity. ULSI design requires a shift in the design paradigm from current evolutionary thinking for system integration, to more of revolutionary approaches as depicted by attributes of if brain architecture.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2000.10014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

The concept of "technology generation" attributed to Gordon Moore has created a plausible method for predicting the behavior of technology road map that has seen world's production of silicon CMOS to exceed 75% of electronic related materials. A feature of such progress is characterized by the complexity factor that predicts the emergence of a new generation of technology every three years.A reasonable method of comparison would be to observe the parallel between CMOS based systems with those of biologically inspired systems. Deep submicron, synonymous with Ultra Large Scale of integration, suggests that by the year 2010 the number of transistors/chip will be in the order of 0.5x10 9 , with an intrinsic clock speed of 3GHz. At this level of integration the classic MOS transistor would have only a few ?electrons' in the channel to direct. Thus, the reality of Quantum MOS (QMOS) transistor becomes a plausible possibility.In the mean time the question remains as to how are we going to cope with the design and quality of the new system complexity. ULSI design requires a shift in the design paradigm from current evolutionary thinking for system integration, to more of revolutionary approaches as depicted by attributes of if brain architecture.
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深亚微米USLI设计范式:谁在书写未来?
戈登·摩尔(Gordon Moore)提出的“技术一代”(technology generation)概念创造了一种合理的方法来预测技术路线图的行为,该路线图已使全球硅CMOS的产量超过75%的电子相关材料。这种进步的一个特点是复杂性因素,它预示着每三年就会出现新一代技术。一种合理的比较方法是观察基于CMOS的系统与生物启发系统之间的并行性。深亚微米,即超大规模集成的代名词,表明到2010年每个芯片的晶体管数量将达到0.5x10 9,固有时钟速度为3GHz。在这种集成水平上,经典的MOS晶体管在沟道中只有几个“电子”要引导。因此,量子MOS (QMOS)晶体管的现实成为一种可能。与此同时,问题仍然是我们将如何处理新系统复杂性的设计和质量。ULSI设计需要设计范式的转变,从当前系统集成的进化思维转向更多的革命性方法,如其大脑架构的属性所描述的那样。
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