{"title":"Autonomous Driving System implemented on Robot Car using SoC FPGA","authors":"A. Kojima","doi":"10.1109/ICFPT52863.2021.9609855","DOIUrl":null,"url":null,"abstract":"We are developing an FPGA-based robot car for the FPT'21 FPGA design competition. The FPGA we are using is Xilinx UltraScale+ MPSoC, which is an SoC type FPGA and mainly consists of a processor part and a programmable logic part. Among the functions of the autonomous driving system, lane-keeping, localization, driving planning, and obstacle avoidance are implemented as software in the processor part. For object detection, Yolo, a machine learning algorithm, is implemented as hardware in the programmable logic part using the DPU IP provided by Xilinx. The PWM circuits for controlling the DC motor and servo motor are also implemented as the original hardware.","PeriodicalId":376220,"journal":{"name":"2021 International Conference on Field-Programmable Technology (ICFPT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Field-Programmable Technology (ICFPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICFPT52863.2021.9609855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We are developing an FPGA-based robot car for the FPT'21 FPGA design competition. The FPGA we are using is Xilinx UltraScale+ MPSoC, which is an SoC type FPGA and mainly consists of a processor part and a programmable logic part. Among the functions of the autonomous driving system, lane-keeping, localization, driving planning, and obstacle avoidance are implemented as software in the processor part. For object detection, Yolo, a machine learning algorithm, is implemented as hardware in the programmable logic part using the DPU IP provided by Xilinx. The PWM circuits for controlling the DC motor and servo motor are also implemented as the original hardware.