HDMI video scaling on an all-programmable SoC

Chih-Yao Tsai, Chaoxiu Chen
{"title":"HDMI video scaling on an all-programmable SoC","authors":"Chih-Yao Tsai, Chaoxiu Chen","doi":"10.1109/ICCPS.2016.7751118","DOIUrl":null,"url":null,"abstract":"We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.","PeriodicalId":348961,"journal":{"name":"2016 International Conference On Communication Problem-Solving (ICCP)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference On Communication Problem-Solving (ICCP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPS.2016.7751118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.
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全可编程SoC上的HDMI视频缩放
我们提出了一种基于全可编程SoC的高清多媒体接口(HDMI)视频缩放系统,该系统可用于任何需要二维插值加速器的图像处理系统。这种结构适用于基于平台的SoC环境。通过AXI视频直接存储器访问(AXI VDMA),视频数据在DDR3存储器和内置FPGA之间直接传输,FPGA实现了所提出的缓冲方案和插值加速器。我们将视频数据存储在DDR3存储器中,插值加速器执行实时视频缩放。通过HDMI视频从一台微软Windows PC机输入,再输出到另一台显示器的实验,验证了实时视频缩放的有效性。
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