A Digital Uncertainty-Tolerant Mismatch Compensation Method in a 17-channel Counter-Sampling Based TDC Architecture

Abstract

A digital calibration method tolerating large uncertainty is proposed in this paper, which effectively ameliorates the code mismatch issues that occur in counter-sampling based time-to-digital converters. The design is based on a 0.11 μm CMOS process. Simulation results show: TDC achieves a resolution of 104 ps. The maximum differential nonlinearity and integral nonlinearity are 0.3 LSB and 2.5 LSB, respectively. An average single shot precision of 52 ps under three different time intervals reflects high uniformity among 17 TDC channels, which is applicable to light detection and ranging systems. This calibration method provides a new idea for metastability-sensitive circuits design.