A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Himanshu Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, S. Borkar
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引用次数: 43

Abstract

High-throughput floating-point computations are key building blocks of 3D graphics, signal processing and high-performance computing workloads [1,2]. Higher floating-point precisions offer improved accuracy at the expense of performance and energy efficiency, with variable-precision floating-point circuits providing run-time precision selection [3]. Real-time certainty tracking enables variable-precision circuits not only to operate at the higher energy efficiency of low-precision datapaths, but also to preserve high-precision accuracy. A variable-precision floating-point unit that performs fused multiply-adds (FMA) with single-cycle throughput while supporting operation in either 1-way single-precision (24b mantissa), 2-way 12b precision or 4-way 6b precision modes is fabricated in 32nm High-k/Metal-gate CMOS [4]. Simultaneous floating-point certainty tracking, preshifted addends, a combined rounding and negation incrementer, efficient reuse of mantissa datapath for multiple parallel lower precision calculations, robust ultra-low voltage circuits, and fine-grained clock gating enable nominal energy efficiency of 52GFLOPS/W (IEEE 32b single-precision, measured at 1.45GHz, 1.05V, 25°C) with a dense layout occupying 0.045mm2 (Fig. 10.3.7) while achieving: (i) scalable performance up to 3.6GFLOPS (single-precision), 96mW measured at 1.2V; (ii) up to 4× higher throughput of 14.4GFLOPS with variable-precision, while maintaining single-precision accuracy; (iii) fast single-cycle precision reconfigurability; (iv) precision mode-dependent power consumption for up to 40% clock power reduction; (v) near-threshold single-precision operation measured at 300mV, 1.75MHz, 11μW; and, (vi) peak energy efficiency of 321GFLOPS/W (single-precision) and 1.2TFLOPS/W (6b precision) at 325mV, 25°C.
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基于32nm CMOS的1.45GHz 52 ~ 162gflops /W可变精度浮点融合乘加单元
高吞吐量浮点计算是三维图形、信号处理和高性能计算工作负载的关键组成部分[1,2]。更高的浮点精度以牺牲性能和能源效率为代价提供更高的精度,可变精度浮点电路提供运行时精度选择[3]。实时确定性跟踪使变精度电路不仅可以在低精度数据路径下以更高的能量效率运行,而且可以保持高精度的精度。采用32nm高k/金属栅CMOS[4]制造的可变精度浮点单元,可在单周期吞吐量下执行融合乘加(FMA),同时支持1路单精度(24b波导),2路12b精度或4路6b精度模式。同时进行浮点确定性跟踪、预移位加数、舍入和负增量、对尾数数据路径的高效重用以实现多个并行低精度计算、鲁棒的超低电压电路和细纹理时钟门控,使其标称能效达到52GFLOPS/W (IEEE 32b单精度,在1.45GHz、1.05V、25°C下测量),其密集布局占用0.045mm2(图10.3.7),同时实现:(i)可扩展性能高达3.6GFLOPS(单精度),在1.2V下测量96mW;(ii)在保持单精度精度的同时,可变精度的吞吐量高达14.4GFLOPS的4倍;(iii)快速单周期精确可重构性;(iv)精密模式相关的功耗高达40%时钟功耗降低;(v)在300mV、1.75MHz、11μW下近阈值单精度工作;(vi)在325mV, 25°C时的峰值能量效率为321GFLOPS/W(单精度)和1.2TFLOPS/W (6b精度)。
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