{"title":"Code generation for compiled bit-true simulation of DSP applications","authors":"L. Coster, M. Adé, R. Lauwereins, J. Peperstraete","doi":"10.1109/ISSS.1998.730590","DOIUrl":null,"url":null,"abstract":"Bit-true simulation verifies the finite word length choices in the VLSI implementation of a DSP application. Present-day bit-true simulation tools are time consuming. We elaborate a new approach in which the signal flow graph of the application is analyzed and then transformed utilizing the flexibility available on the simulation target. This global approach outperforms current tools by an order of magnitude in simulation time.","PeriodicalId":305333,"journal":{"name":"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)","volume":"60 14","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSS.1998.730590","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
Abstract
Bit-true simulation verifies the finite word length choices in the VLSI implementation of a DSP application. Present-day bit-true simulation tools are time consuming. We elaborate a new approach in which the signal flow graph of the application is analyzed and then transformed utilizing the flexibility available on the simulation target. This global approach outperforms current tools by an order of magnitude in simulation time.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
