A 1.1 ∼ 2.9 GHz High Efficiency CMOS Power Amplifier

Abstract

This paper describes a CMOS power amplifier (PA). It discusses how to compromise the size and structure of the transistor in the design of the power amplifier, and to elaborate on the design of the transistor for the parasitics when the frequency increases. The power amplifier designed in this paper adopts a two-stage cascade structure. It works in the Class-AB state. It uses the third-order Chebyshev network for output impedance matching to achieve large saturation power output. A third-order Butterworth network is used as the inter-stage matching, and achieves high power transmission efficiency from the driver stage to the power stage through a Norton transformation. This paper also discusses how to further widen the bandwidth of the power amplifier as well as improving the linearity. Simulation results shows that, the output saturation power (Psat) is greater than 25.5 dBm from 1.1 GHz to 2.9 GHz, the maximum Psat is 27.6 dBm, and the peak power added efficiency (PAE) is 34.9% ∼ 49.4%.