N. Kawato, Takao Saito, Fumihiro Maruyama, T. Uehara
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引用次数: 23
Abstract
This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.
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