A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI:10.1145/1013235.1013300

Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu

引用次数: 16

Abstract

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 /spl mu/m process parameters, the results show that INL < /spl plusmn/0.4 LSB and DNL < /spl plusmn/0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

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基于一种新型互补平均值方法的低功耗轨对轨6位闪存ADC

本文提出了一种6位300 msample /s(MS/s)的flash模数转换器(ADC)，该转换器采用一种新颖的互补平均值(CAV)方法。输入信号经过预处理，然后转向与固定的参考电压电平进行比较，大大简化了比较器的设计，从而降低了功耗。此外，所提出的CAV技术可以实现轨道到轨道的输入范围，并且由于比较器的操作条件安排相似，因此可以最小化偏移和气泡误差。采用台积电1P5M 0.25 /spl mu/m工艺参数进行仿真，结果表明，INL < /spl plusmn/0.4 LSB, DNL < /spl plusmn/0.1 LSB, SNDR为32.7dB。该转换器在2.5 V电源下消耗35mW，该转换器的功率效率仅为3.3pJ/ convo -step，与其他已发表的结果相比具有优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

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