Hardware simulation with software modeling for enhanced architecture performance analysis

Abstract

Complex simulation-based design efforts suffer from lengthy simulations. It becomes difficult to develop and debug hardware models when the turn around time between development and test results are measured in terms of days or even weeks. A significant lag between development and architecture performance test results cast severely hamper the design effort. A strategy for accurate rapid modeling of a complex digital design is presented The precision of a cycle accurate hardware description language (HDL) model was combined with the speed of software modeling to provide rapid system performance evaluation. The hardware model was used to generate timing information and resource requirements from a limited data set. These results were back annotated into the existing algorithm written in a high-level programming language, in order to generate realistic, full system, performance parameters and thus quickly assess the satisfaction of performance constraints by the chosen architecture.