Low-Power Multipliers with Data Wordlength Reduction

Abstract

Multiprecision multipliers reduce power consump- tion by selecting smaller multipliers (i.e., submultiplier) according to the wordsize of the input operands. However, arbitrary levels of bit precision are not achieved by multiprecision multipliers. Two proposed wordlength reduction techniques that reduce power consumption with arbitrary levels of bit precision are considered. Expectation values of bit switching activity for reduction in the signed right shift method and the truncation method are derived. The signed right shift method and the truncation method are applied to a 16-bit radix-4 modified Booth multiplier and a 16-bit Wallace multiplier. The truncation method with 8-bit operands reduces the power consumption by 56% in the Wallace multiplier and 31% in the Booth multiplier. The signed right shift method shows no power reduction in the Wallace multiplier and 25% power reduction in the Booth multiplier. Unequal levels of precision in operands show different power reduction value for the Booth multiplier. The non-recoded operand in the Booth multiplier with 8-bit reduction has 13% more sensitivity in power consumption than the recoded multiplicand.