VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS

Abstract

In this paper we propose a new hybrid analytical-empirical model, called VAR-TX, that exhaustively computes and compares all feasible architectures subject to inter-die (DID) and intra-die (WID) process variations (PV). Based on its computation, VAR-TX predicts the optimal architecture that provides minimum access-time and minimum access-time variation for yield enhancement in future 16-nm on-chip conventional six-transistor static random access memories (6T-SRAMs) of given input specifications. These specifications include SRAM size and shape, number of columns, and word-size. We compare the impact of D2D and WID variations on access-time for 16-nm SRAM with the 45-nm and 180-nm nodes and demonstrate that the drastic increase in the 1- and 3-sigma of the smaller nodes is mainly due to the increase in the WID variations. Finally, our model disputes previously published works-suggesting that square SRAM always produces minimum delays-and significantly extends and enhances the older models by adding both an extra dimension of architectural consideration and additional device parameter fluctuation to the analysis, while producing delay estimates within 4% of Hspice results.