{"title":"Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC","authors":"Abhisek Dey, T. K. Bhattacharyya","doi":"10.1109/SOCC.2011.6085099","DOIUrl":null,"url":null,"abstract":"A low power 1.3V 12bit successive approximation register analog-to-digital converter (SAR ADC) is presented for MEMS and biomedical applications. In the DAC of this ADC, a new switch control technique has been proposed to make the ADC more energy as well as area efficient. Besides, a very high resolution, low offset CMOS comparator is designed for the satisfactory operation of the ADC. The complete ADC has been implemented using UMC 0.18µm RF/CMOS process with 1.8V supply voltage and 1.3V reference voltage for the DAC. Its performance has been verified by spectre simulation. The ADC achieved a sampling rate of 120KSPS and a power consumption of 3mW at 1.8V supply voltage. Its DNL and INL are 0.68LSB and 0.7LSB respectively.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085099","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A low power 1.3V 12bit successive approximation register analog-to-digital converter (SAR ADC) is presented for MEMS and biomedical applications. In the DAC of this ADC, a new switch control technique has been proposed to make the ADC more energy as well as area efficient. Besides, a very high resolution, low offset CMOS comparator is designed for the satisfactory operation of the ADC. The complete ADC has been implemented using UMC 0.18µm RF/CMOS process with 1.8V supply voltage and 1.3V reference voltage for the DAC. Its performance has been verified by spectre simulation. The ADC achieved a sampling rate of 120KSPS and a power consumption of 3mW at 1.8V supply voltage. Its DNL and INL are 0.68LSB and 0.7LSB respectively.
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