n /spl times/ n carry-save multipliers without final addition

P. Montuschi, L. Ciminiera
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引用次数: 5

Abstract

Carry-save multipliers require an adder at the last step to convert the carry-sum representation of the most significant half of the result into an irredundant form. A multiplication scheme where by this conversion is performed with a circuit operating in parallel with the carry-save array is presented. The resulting implementation, when a radix-2 adder array is used, produces a result on 2n bits with a delay comparable to that of the multiplier proposed by M.D. Ercegovac and T. Lang (1990). When a radix-4 array is used, the proposed unit is almost twice as fast as units proposed previously.<>
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N /spl倍/ N个无最终加法的进位乘法器
免进位乘法器在最后一步需要加法器来将结果的最有效一半的进位和表示转换为不冗余的形式。提出了一种乘法方案,其中通过与进位保存阵列并行操作的电路来执行这种转换。当使用基数为2的加法器阵列时,产生的结果为2n位,其延迟与M.D. Ercegovac和T. Lang(1990)提出的乘法器相当。当使用基数为4的数组时,建议的单位几乎是以前建议的单位的两倍。
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