Radiation-hardened Test Design for Aerospace SoC

Abstract

Due to space application scenarios, radiation hardening techniques should be applied on aerospace SoC. This paper introduces an integrated test method for radiation-hardened SoC, which combines traditional scan chain and Memorybist designs, and new TMD chain and RAM test designs to verify the performance of rad-hardened SoC. The design of scan chain and Memorybist can be applied to the rapid screening of chips after tapeout. TMD chain and RAM test can verify the radiation-hardened performance of the chip in radiation experiments. The whole test design is flexible and configurable with high test coverage, and it is helpful to analyze the malfunction and radiation resistance of the chip.