Using Karnaugh Maps in Software Requirements Analysis

A. Cantone, Yawa E. Adonsou
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Abstract

Faulty requirements leading to design deficiencies have been shown to be an avoidable root cause of many product failures. This paper is an effort to push the boundaries of system safety by proposing a novel approach for discovering faulty or missing software requirements by adapting a proven methodology heretofore used in circuit analysis. Karnaugh Mapping is employed in Application-Specific Integrated Circuit (ASIC) design to minimize power consumption, facilitate temperature control, increase functionality and minimize the number of physical logic gates. Karnaugh Maps (K-Maps) are ideally suited to impose order on logical requirements that describe the operation of electronic circuits. With the assumption that software requirements are expressible as logical statements, this paper assesses the ability of Karnaugh Mapping to effectively deconstruct and rationalize developmental requirements in the analysis of software and seeks to demonstrate that K-Maps can be used not only to minimize the number of requirements, but also to detect missing requirements. The analysis conducted in the course of developing this paper indicates that K‑Maps can effectively identify faulty requirements in two examples of varying complexity, provided that sematic conventions are established and observed.
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在软件需求分析中使用卡诺图
错误的需求导致设计缺陷已经被证明是许多产品失败的一个可避免的根本原因。本文通过采用一种迄今为止在电路分析中使用的经过验证的方法,提出一种新的方法来发现错误或缺失的软件需求,从而努力推动系统安全的界限。卡诺映射用于专用集成电路(ASIC)设计,以尽量减少功耗,便于温度控制,增加功能并尽量减少物理逻辑门的数量。卡诺图(k - map)非常适合于对描述电子电路操作的逻辑要求施加秩序。假设软件需求可以用逻辑语句表达,本文评估了Karnaugh Mapping在软件分析中有效解构和合理化开发需求的能力,并试图证明K-Maps不仅可以用来最小化需求的数量,还可以用来检测缺失的需求。在本文开发过程中进行的分析表明,只要建立并遵守语义约定,K - Maps可以在两个不同复杂性的示例中有效地识别错误需求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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