Power Reduction of ITC'99-b01 Benchmark Circuit Using Clock Gating Technique

Abstract

This paper, deals with Latch Free Clock Gating technique for reduction of clock power and dynamic power consumption in ITC'99 bo1 Benchmark circuit and we have compared power reduction at different device operating frequencies. Without latch free clock gating technique in b01 benchmark circuit the Contribution of Clock power was 37.50%, 37.64%, 4.46%, 38.75% and 38.76% of total dynamic power when device is operating at frequency 100MHz, 1GHz, 10GHz, 100GHz and 1 THz respectively. After implementation of latch free clock gating technique, In b01 benchmark circuit, Clock power contribution in total dynamic power reduces to 1.96%, 1.98%, 1.93% and 1.92%, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz respectively. We synthesized this device on 40-nm vertex-6 this technique also reduces significantly IOs power. We have shown last results only at two operating frequency i.e. 10GHz and 100GHz. At operating frequency of 1 THz, the proposed design results 97.08 % reduction in clock power, 7.28% reduction in IOs power and 44% reduction in dynamic power as compare d to ITC'99 b01 benchmark circuit without latch free clock gating technique.