An easy approach to formal verification

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.616990

T. Schlipf, T. Buchner, R. Fritz, M. Helms

引用次数: 3

Abstract

Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.

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一种简单的形式验证方法

形式验证被认为是复杂的，需要大量的数学背景才能成功应用。本文描述了一种将形式验证(FV)添加到验证过程的方法，而不需要任何形式验证语言的知识。它只使用有限状态机符号，这对设计人员来说是熟悉和直观的。FV的另一个问题是状态空间爆炸。如果发生这种情况，我们可以在一个小时内切换到随机模拟，而不会失去任何努力。结果表明，FV至少与随机模拟一样快，并且由于它是穷举的，在验证质量方面具有优越性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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