Design of a high speed and low area latch-based comparator in 90-nm CMOS technology having low offset voltage

Abstract

A comparator is the essential building block of any analog-to-digital circuit. They generally are the decision-making circuits that play a key role in the analog to digital conversion; hence the accuracy and speed are the characteristics that are considered. Dynamic comparators are thus most widely used. This paper puts forth the design of a latch-based comparator which has very less delay, high speed, low area and less offset voltage, in comparison to the conventional comparators. The power dissipation is also less of the proposed circuit. The design and analysis (simulation) has been done using Cadence tool in 90-nm CMOS technology.