A PLL with high-speed operating discrete loop filter

Seong-Jin An, Young-Shig Choi
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Abstract

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator’s output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional 2 nd -order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and ‘on/off’ depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.
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带高速工作离散环路滤波器的锁相环
本文提出的小尺寸锁相环在压控振荡器输出信号控制的离散环滤波器下工作稳定。在锁相环中引入了开关控制环滤波器,取代了传统的二阶环滤波器。这三个开关由压控振荡器的高频输出信号控制。开关也由UP/DN信号和“开/关”控制,这取决于UP/DN信号的存在。带开关的负反馈功能电容器确实可以将锁相环集成到单个芯片中。即使在离散环路滤波器中使用了总共180pF的小电容,所提出的锁相环也能稳定工作。该锁相环采用1.8V电源电压、0.18um多金属和多层CMOS工艺设计,并通过Hspice仿真验证。
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