Throughput enhancement in multiprocessor architectures for pipelining and digital signal processing applications

Abstract

The authors discuss throughput enhancement for pipelining and digital signal processing applications in a multiprocessor environment. A common objective in pipelining and digital signal processing is the repeated execution of the same computational job consisting of a set of computational operations with high throughput or sampling rates. For good performance and avoidance of internal conflicts, the concurrent computational operations of successive data sets of a computational job should be properly scheduled. Heuristic suboptimal scheduling algorithms are developed whose execution time is a polynomial function of the number of items to be scheduled. Insertion of delay is used as a basic tool for better utilization of hardware, thereby increasing the throughput. Rescheduled computational jobs are directed to architectures consisting of arbitrary number of processors. Simulation results are presented.<>