Design of a novel error detection and correction scheme for pipeline and other multi-stage ADCs with a mono comparator per stage pipeline like architecture

Abstract

The paper describes a novel design that minimizes the effect of small offset errors in comparators of pipeline ADCs. This simple but effective error detection and correction scheme enables to eliminate the requirement of redundant comparators in the stages of a Pipeline ADC. A one bit per stage pipeline like architecture is also proposed. Implementing a single bit per stage design, using mono comparator per stage architecture leads to lower power consumption and eliminates the extra cost involved for redundant bits in a pipeline ADC. This error detection scheme is capable of minimizing error in Algorithmic, Successive Approximation or other multi stage or multi step ADCs. The proposed scheme was simulated as well as implemented in hardware using various discrete components and ICs. The developed error correction logic works properly for small comparator offset errors and exhibits fairly accurate results in simulation and as well as in hardware implementation. The designs, if fabricated in IC form, can be a low cost low power alternative to conventional pipeline architectures with a high resolution at a high speed with reasonably good accuracy, though requiring less area and consuming less power.