{"title":"Investigation of effectiveness of split image plane for ESD immunity in system level","authors":"Yuang-Shung Lee, Cheng-Hsiung Chiang","doi":"10.1109/INTLEC.2009.5352011","DOIUrl":null,"url":null,"abstract":"In recently years, high speed digital circuit equipment and products with electrostatic discharge (ESD) issues have become crucial due to tighter rise time and smaller geometry spacing. A typical ESD trouble shooting case is discussed involving a personal computer system followed with plain analysis to confirm the ESD interference path in a complex system. Further analysis studies several printed circuit board (PCB) structure traces relative to crosstalk. The target ESD immunity is then increased up from ±4kV to ±6kV contact discharge for the margin design to ensure the improved effect using a novel technique in this evaluated system. The simulation result is verified to be in good agreement with the measurement result.","PeriodicalId":445164,"journal":{"name":"INTELEC 2009 - 31st International Telecommunications Energy Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"INTELEC 2009 - 31st International Telecommunications Energy Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INTLEC.2009.5352011","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In recently years, high speed digital circuit equipment and products with electrostatic discharge (ESD) issues have become crucial due to tighter rise time and smaller geometry spacing. A typical ESD trouble shooting case is discussed involving a personal computer system followed with plain analysis to confirm the ESD interference path in a complex system. Further analysis studies several printed circuit board (PCB) structure traces relative to crosstalk. The target ESD immunity is then increased up from ±4kV to ±6kV contact discharge for the margin design to ensure the improved effect using a novel technique in this evaluated system. The simulation result is verified to be in good agreement with the measurement result.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
