Tensor decomposition over a Fast-Prototyping HCP composed by CPU-GPU

Abstract

Tensor decomposition has gained special attention in modern implementations for wide range of digital signal processing (DSP) areas. This decomposition has a transcendental role because most of DSP systems have a better representation when using models indexed with more than two indexes. The main drawback is that Tensor decomposition is a computationally-demanding algorithm and ad-hoc designs and implementations are costly and require long design periods. This paper presents the prototyping of Tensor decomposition as a proof-of-concept (PoC) over a high-performance CPU-GPU Heterogeneous Computing Platform (HCP)-based DSP blocks exposing variable levels of parallelism, throughput, resource utilization and with a modular approach that eliminates the overhead of designing ad-hoc architectures. Benefits of using the modular approach of this prototyping platform for implementing the Tensor decomposition is clear as the design time reduces and a clear idea of particular requirements for a final implementation is obtained from early stages of the PoC development.