Standard VHDL analyzer and intermediate representation

Abstract

To research and develop Computer Aided Design (CAD) tools based on VHDL, an analyzer is necessary to translate the source code into an intermediate representation from which back-end tools can be developed. Whether the analyzer is purchased or built, it is secondary to the research, diverting cost and effort from the intended development. The existence of a standard intermediate representation and a freely available VHDL analyzer that translates source code to that representation allows resources to be focused on the productivity enhancing, back-end tools. The SAVANT project provides VHDL researchers with the tools and compatibility to achieve a significant enhancement in the overall effectiveness of basic CAD-in-VHDL research.