{"title":"A 5.8 GHz CMOS low noise amplifier for electronic toll collection system","authors":"Siheng Zhu, Chao Guo, Kun Feng, Jingjing Zou, Houjun Sun, X. Lv","doi":"10.1109/ICMMT.2012.6229963","DOIUrl":null,"url":null,"abstract":"This paper presents a 5.8 GHz low noise amplifier (LNA) for electronic toll collection system (ETCS). Traditional design strategy of source inductor feedback amplifier (L-CSLNA) ignores the influence of off chip matching, such as print circuit broad (PCB), bonding wire and passive chip parts which greatly affect the performance of LNA at high frequency. In this paper we adopt 3D electromagnetic simulation to analyze the impacts of off chip components to the design of LNA. The proposed LNA has been fabricated in 0.18 μm CMOS process. The measured S11 of the proposed LNA is less than -10 dBm from 5.7 to 5.9 GHz, the minimal noise figure (NF) is 2 dB, the maximal power gain is 12.7 dB and the IIP3 is -4 dBm with 16 mW power dissipation.","PeriodicalId":421574,"journal":{"name":"2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMMT.2012.6229963","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents a 5.8 GHz low noise amplifier (LNA) for electronic toll collection system (ETCS). Traditional design strategy of source inductor feedback amplifier (L-CSLNA) ignores the influence of off chip matching, such as print circuit broad (PCB), bonding wire and passive chip parts which greatly affect the performance of LNA at high frequency. In this paper we adopt 3D electromagnetic simulation to analyze the impacts of off chip components to the design of LNA. The proposed LNA has been fabricated in 0.18 μm CMOS process. The measured S11 of the proposed LNA is less than -10 dBm from 5.7 to 5.9 GHz, the minimal noise figure (NF) is 2 dB, the maximal power gain is 12.7 dB and the IIP3 is -4 dBm with 16 mW power dissipation.
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