Recessed gate junction field effect transistors

Abstract

A recessed gate structure is described for vertical channel junction gate field effect transistors. This structure can be fabricated using a self-aligned source-gate process with the use of only two masking steps for the fabrication of the device active region. Devices fabricated with this structure exhibit blocking voltages of upto 400 volts with blocking gains ranging from 3 to 12 depending upon the groove depth. These devices have a unity power gain cut-off frequency above 500 MHz.