A CMOS Reference Voltage Buffer Designed for Near-rail Voltage

Qihao Yin, Chunfeng Bai
{"title":"A CMOS Reference Voltage Buffer Designed for Near-rail Voltage","authors":"Qihao Yin, Chunfeng Bai","doi":"10.1109/ICICM50929.2020.9292131","DOIUrl":null,"url":null,"abstract":"This paper presents a CMOS buffer for near-rail voltage. Compared with conventional OTA-based structure, an additional super source follower is added in the loop, which hence maintains fairly high loop-gain even when the input voltage is very close to the power supply voltage or ground. The voltage-drop between the buffered voltage and the rail can be as low as 10 mV. Besides, the output impedance can be lower as the proposed buffer entails larger load capacitor.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292131","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

This paper presents a CMOS buffer for near-rail voltage. Compared with conventional OTA-based structure, an additional super source follower is added in the loop, which hence maintains fairly high loop-gain even when the input voltage is very close to the power supply voltage or ground. The voltage-drop between the buffered voltage and the rail can be as low as 10 mV. Besides, the output impedance can be lower as the proposed buffer entails larger load capacitor.
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近轨电压CMOS参考电压缓冲器设计
本文提出了一种CMOS近轨电压缓冲器。与传统的基于ota的结构相比,在环路中增加了一个超级源从动器,因此即使在输入电压非常接近电源电压或地时,也能保持相当高的环路增益。缓冲电压与导轨之间的压降可低至10mv。此外,由于所提出的缓冲器需要更大的负载电容,因此可以降低输出阻抗。
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