Implementation of a Spiking Neuron in CMOS

Abstract

A spiking neuronal network consumes very low power for computation contrary to conventional Von-Neumann architectures. A CMOS based circuit which includes several features of a spiking neuron closely, is presented in this paper. Features such as refractory period, spike height and width, resting potential, spiking threshold, spike frequency adaptation and inter spike interval (ISI) have been incorporated in the circuit. A small set of parameters, chosen carefully control these features in the circuit response. The spiking pattern of the proposed circuit has been matched with selected experimental data of real biological neurons from Allen Institute for Brain Science (AIBS) database.