Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning

Abstract

Technology mapping from logic netlists to programmable logic blocks (PLB) plays an important role in FPGA EDA flow, especially for architecture exploration of PLBs. However, technology mapping becomes time-consuming due to the booming scale and complexity of IC designs as well as the growing complexity of PLB architectures. To speed up this process, a parallelized technology mapping approach based on adaptive circuit partitioning is proposed in this paper to perform fast multi-thread technology mapping. First, We choose the best of the three candidate partitioning strategies for the given netlist by circuit analysis to partition the original netlist into several independent sub-netlists. Secondly, these sub-netlists are mapped to the given PLB architecture simultaneously in their corresponding mapping threads. Finally, the complete mapped netlist is generated by merging the mapped sub-netlists. The proposed approach is implemented in ABC, independent of the detailed mapping algorithm. 13 large circuits from the Titan23 benchmark set are used as benchmarks to evaluate the proposed approach. Experimental results show that the proposed approach leads to an average of 5.76 × speedup over the single-thread version (up to 8.21 × individually) with no delay loss and less than 0.57% average area penalty.