High-speed data acquisition system based on AVR and CPLD

Abstract

In order to improve the speed of data acquisition card,while reducing costs,the parallel data acquisition system is designed,which requires a parallel acquisition speed is greater than 10 Mb/s.The system consists of AVR and the CPLD control implementation,through a MAX1308 ADC completion of the transformation process,and is designed to build its peripheral circuits.Using a 12-channel data storage mode for high-speed data acquisition storage,experimental basis for the storage requirements to build and debug the hardware circuit,the oscilloscope waveform displays the results of pulse sequences of their eight groups,there was no temporal chaos in parallel processing,and does not interact to achieve a low-cost high-speed multi-channel acquisition design requirements.