Parallel CN-VN processing for NB-LDPC decoders

Hassan Harb, Cédric Marchand, L. Conde-Canencia, E. Boutillon, A. Ghouwayel
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引用次数: 1

Abstract

In this paper, a novel and innovative approach to implement the check node and variable node phases of the EMS algorithm is proposed. The novelty is not only from the hardware side, but also from the algorithmic point of view. An unusual manner of processing some steps of the check and variable nodes are shown. The performance and implementation results are promising to dig deeper in this work. Compared to its serial counterpart, the synthesis results of the proposed architecture show a factor gain greater than two in terms of area efficiency, with negligible performance loss.
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NB-LDPC解码器的并行CN-VN处理
本文提出了一种新颖而创新的方法来实现EMS算法的检查节点和可变节点阶段。其新颖性不仅体现在硬件方面,还体现在算法方面。显示了处理检查和变量节点的一些步骤的一种不寻常的方式。性能和实现结果有望在这项工作中深入挖掘。与串行对应物相比,所提出架构的综合结果显示,就面积效率而言,增益系数大于2,性能损失可以忽略不计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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