On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies

Abstract

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit (IC) design is proposed and targeted to state-of-the-art layout-aware circuit-sizing flows. The multi-objective optimization (MOO)-based placement templates generator (PTG) inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, that fit the current state of the optimization process and are used within the layout-aware methodology to generate the floorplan of the following tentative solutions. This innovative methodology combines the advantages of previous template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of Pareto set. Moreover, as the PTG runs in parallel with the layout-aware loop, it has no impact on the layout-aware execution time. Experimental results present solutions with 47% less area when compared to a multi-template layout-aware approach.