Fabrication and performance of InP MISFET

T. Kawakami, M. Okamura
{"title":"Fabrication and performance of InP MISFET","authors":"T. Kawakami, M. Okamura","doi":"10.1109/IEDM.1980.189862","DOIUrl":null,"url":null,"abstract":"N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.
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InP MISFET的制造与性能
采用以下制造技术,已开发出用于高增益和高速应用的n沟道常关InP misfet:(1)将硫扩散工艺应用于p和半绝缘InP晶片中,用于n沟道FET的低阻源极和漏极。(2)Al2O3CVD法在InP衬底上的制备。(3)在半绝缘InP衬底表面形成n沟道。(4)消除栅极漏极和栅极源寄生电容的伪自对准技术。研究了电导和漂移特性,并进行了MIS二极管电容测量和AES分析。
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