The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation

Abstract

In this paper, we present a fast architecture of realtime CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub- modules and multi sub-symbol decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30 fps for 1080 p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5 ns.