DC blocking capacitor interfacing for high speed communication buses

Abstract

This paper studies integration aspects of DC blocking capacitors in differential high speed bus channels. The presence of a DC blocking capacitor in the signal path can present an impedance mismatched medium which can lead to signal degradation. Integrating the capacitor to minimize impedance mismatches becomes of high importance. The differential impedance of a micro-strip differential pair is evaluated in simulation under different physical design conditions. Additionally, test vehicle measurements for a variety of capacitor test sites with different characteristics including: package size, voiding scenarios under capacitor pads/packages and wiring layers for traces to the capacitors has been designed and fabricated. The test sites are measured up to 20GHz using a VNA and their results are discussed. Also, several of the test sites are simulated in order to validate the modelling method for future design analysis purposes.