{"title":"A 0.6V 70-dB SNDR energy efficient hearing aid current mode readout amplifier using accuracy compensation and adaptive bias current techniques","authors":"Fanyang Li, Tao Yang","doi":"10.1109/ICCPS.2016.7751094","DOIUrl":null,"url":null,"abstract":"An energy efficient hearing aid current mode readout amplifier using accuracy compensation and adaptive bias current techniques is presented, for the improved accuracy with the saved power. Compared with the conventional current mode amplifiers, the amplifier with the techniques is characterized by the pole-zero canceling feedback loop and the adaptive current mode feedback loop. With the techniques, the accuracy and power dissipation can be simultaneously optimized. Simulated with a 0.18 μm CMOS process, with the typical 0.6V supply voltage, the signal to noise and distortion rate (SNDR) achieves 70dB@4μAp-p output current. Moreover, the power consumption is maintained within 27 μ W.","PeriodicalId":348961,"journal":{"name":"2016 International Conference On Communication Problem-Solving (ICCP)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference On Communication Problem-Solving (ICCP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPS.2016.7751094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An energy efficient hearing aid current mode readout amplifier using accuracy compensation and adaptive bias current techniques is presented, for the improved accuracy with the saved power. Compared with the conventional current mode amplifiers, the amplifier with the techniques is characterized by the pole-zero canceling feedback loop and the adaptive current mode feedback loop. With the techniques, the accuracy and power dissipation can be simultaneously optimized. Simulated with a 0.18 μm CMOS process, with the typical 0.6V supply voltage, the signal to noise and distortion rate (SNDR) achieves 70dB@4μAp-p output current. Moreover, the power consumption is maintained within 27 μ W.