{"title":"A distributed backpropagation algorithm of neural networks on distributed-memory multiprocessors","authors":"H. Yoon, J.H. Nang, S. Maeng","doi":"10.1109/FMPC.1990.89482","DOIUrl":null,"url":null,"abstract":"A distributed backpropagation algorithm for a fully connected multilayered neural network on a distributed-memory multiprocessor system is presented. The neurons on each layer are partitioned into p disjoint sets, and each set is mapped on a processor of a p-processor system. The algorithm, the communication pattern among the processors, and their time/space complexities are investigated, and the theoretical upper bound on speedup is obtained. The experimental speedup obtained with the algorithm on a ring of 32 transputers, which confirms the model and analysis, is reported. It is found that the choice of processor interconnection topology does not influence the speedup ratio.<<ETX>>","PeriodicalId":193332,"journal":{"name":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1990.89482","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
A distributed backpropagation algorithm for a fully connected multilayered neural network on a distributed-memory multiprocessor system is presented. The neurons on each layer are partitioned into p disjoint sets, and each set is mapped on a processor of a p-processor system. The algorithm, the communication pattern among the processors, and their time/space complexities are investigated, and the theoretical upper bound on speedup is obtained. The experimental speedup obtained with the algorithm on a ring of 32 transputers, which confirms the model and analysis, is reported. It is found that the choice of processor interconnection topology does not influence the speedup ratio.<>
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