Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems

Abstract

Nowadays, embedded systems are ubiquitous and their functionality is becoming increasingly intertwined with various critical demands. Integrating functionality with different criticality demands has led to the emergence of mixed-criticality systems (MCS), which require adaptive fault tolerance to ensure the correctness of critical tasks. In this paper, we propose a hardware-based adaptive redundancy approach for multi-core systems, which aims to enhance the reliability and safety of MCS. Our approach involves the reconfiguration of two physical processor cores into a single logical core that executes the same program on demand. The logical core provides adaptive redundancy to detect and mask faults. However, this reconfiguration can potentially result in deadlocks. To address this issue, we identify the scenarios where deadlocks may occur and provide a countermeasure to prevent their emergence. By adopting this runtime adaptive and hardware-based adaptive redundancy method, we can improve the reliability and safety of mixed-criticality systems. At the same time we utilize the processor architecture to abstract the reconfiguration process.