Interconnection complexity study for a piggy back WSHP GaAs systolic processor

Abstract

The impact of interprocessor communication complexity in systolic arrays is considered. These issues are explored in the context of the design for a compact processor capable of processing 1000 billion systolic operations per second. The goal is to realize the processor in a compact wafer scale hybrid package (WSHP) using sixteen 8-in-diameter wiring substrates with roughly 70 systolic processor cells mounted in piggyback fashion on top of them. It is shown that except in the simplest cases the interprocessor wiring substrate may require some form of repair strategy to be fabricatable. In any case, some means for testing the substrate wiring will be required. The use of a focused ion beam and a means of accomplishing test and repair for a passive wiring substrate is briefly examined.<>