Parallelism tuning according to the deadline for power-gated ILP processors

Abstract

Digital signal processors (DSP) with very-longinstruction-word (VLIW)processors have been widely used incommunication systems in recent years. It is obvious that parallelism requirement are different between applications, even within an application. As a result, the scheme, which is to partition the application into several regions and assign each region with adapted parallelism, has been proposed. In this paper, we enhance the parallelism assignment stage. The aim is to tune parallelism according to the deadline (the special execution time of users). The proposed algorithm could save more energy with meeting the requirement of users. The experimental results of evaluation with CoreMarkPro benchmark suits show the expected savings of leakage energy. Compared with maximum energy mode, the execution energy could be reduced more than 40% and the execution time just increase less than 10%.