D. Ogden, B. Kuttanna, A. Loper, S. Mallick, M. Putrino
{"title":"A new PowerPC microprocessor for low power computing systems","authors":"D. Ogden, B. Kuttanna, A. Loper, S. Mallick, M. Putrino","doi":"10.1109/CMPCON.1995.512397","DOIUrl":null,"url":null,"abstract":"A new PowerPC microprocessor is designed for desktop companions and high end embedded multimedia applications such as high performance video games with graphics intensive operations. It features a low power consumption of 1.2 watts at 66 MHz at 3.3 volts. The processor is fabricated in a 0.5 micron, 4 level metal CMOS technology resulting in 1 M transistors in a 7.07 mm by 7.07 mm chip size. Dual 4K-byte instruction and data caches coupled to a high performance 64-bit multiplexed bus and separate execution units (branch, float, integer, and load-store units) result in a peak instruction rate of 2 instructions per clock cycle. Low power techniques are used throughout the entire design including dynamically powered down execution units.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1995.512397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A new PowerPC microprocessor is designed for desktop companions and high end embedded multimedia applications such as high performance video games with graphics intensive operations. It features a low power consumption of 1.2 watts at 66 MHz at 3.3 volts. The processor is fabricated in a 0.5 micron, 4 level metal CMOS technology resulting in 1 M transistors in a 7.07 mm by 7.07 mm chip size. Dual 4K-byte instruction and data caches coupled to a high performance 64-bit multiplexed bus and separate execution units (branch, float, integer, and load-store units) result in a peak instruction rate of 2 instructions per clock cycle. Low power techniques are used throughout the entire design including dynamically powered down execution units.