A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery

T. Sakata, T. Hirotsu, H. Yamada, T. Kataoka
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引用次数: 16

Abstract

A cost-effective, dependable microcontroller architecture has been developed. To detect soft errors, we developed an electronic design automation (EDA) tool that generates optimized soft error-detecting logic circuits for flip-flops. After a soft error is detected, the error detection signal goes to a developed rollback control module (RCM), which resets the CPU and restores the CPU's register file from the backup register file using a rollback program routine. After the routine, the CPU restarts from the instruction executed before the soft error occurred. In addition, there is a developed error reset module (ERM) that can restore the RCM from soft errors. We also developed an error correction module (ECM) that corrects ECC errors in RAM after error detection with no delay overheads. Testing on a 32- bit RISC microcontroller and EEMBC benchmarks showed that the area overhead was under 59% and frequency overhead was under 9%. In a soft error injection simulation, the MTBF of random logic circuits, and the MTBF of RAM were 30 and 1.34 times longer, respectively, than those of the original microcontroller.
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一种具有指令级回滚的低成本可靠的微控制器体系结构,用于软错误恢复
开发了一种经济、可靠的微控制器体系结构。为了检测软错误,我们开发了一个电子设计自动化(EDA)工具,该工具可以为触发器生成优化的软错误检测逻辑电路。在检测到软错误后,错误检测信号将转到开发的回滚控制模块(RCM), RCM复位CPU,并使用回滚程序例程从备份寄存器文件中恢复CPU的寄存器文件。例程后,CPU从软错误发生前执行的指令重新启动。此外,还有一个开发的错误重置模块(ERM),可以从软错误中恢复RCM。我们还开发了一个纠错模块(ECM),在错误检测后纠正RAM中的ECC错误,没有延迟开销。在32位RISC微控制器和EEMBC基准测试上的测试表明,面积开销低于59%,频率开销低于9%。在软错误注入仿真中,随机逻辑电路的MTBF和RAM的MTBF分别是原始微控制器的30倍和1.34倍。
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