An area efficient high speed optimized FFT algorithm

Abstract

In recent years the Fast Fourier Transform is widely used in a number of applications as it is considered to be an efficient algorithm to compute the Discrete Fourier Transform. The process of computing the FFT for large sequence real time data becomes complex and tedious. Hence it is necessary to design a system that can perform the FFT computation of large sequence data with reduced power consumption. This paper presents the design of low power Radix-8 DIT FFT. The proposed design aims at reducing the number of multipliers that are used to compute the FFT. This is achieved by swapping the input terms and reordering them. This leads to a reduction in the number of multipliers used to perform the computation and thereby causing a reduction in the power consumption. This method is highly advantageous when the input signals are lengthy since the number of multipliers used is large in number consuming very high power. In order to optimize the FFT architecture the number of multipliers is reduced thereby causing a significant reduction in power. The prototype for Radix-2 (8 point) and Radix-4 (16 point) optimized FFT is designed, implemented and simulated using Altera ModelSim DE2 EP2C35F672C6 FPGA device. The proposed Radix-2 (8 point) and Radix-4 (16 point) optimized FFT operates at a speed of 10.41 Gbps and 21.23 Gbps respectively.