A Machine Learning-Based Error Model of Voltage-Scaled Circuits

Abstract

Various approximation methods demonstrate the effectiveness of voltage scaling in digital circuits in order to explore the energy-error trade-off. An accurate error model is of critical importance for assessing the error behavior of voltage-scaled circuits and its effects on the application quality. However, existing error models of voltage-scaled circuits overlook the effects of input data and error rate disparity among different bits. To tackle this challenge, we propose a machine learning-based error model of voltage-scaled circuits that can predict the timing error rate for each output bit. We train this model using random forest methods with input features and output labels extracted from gate-level simulation. We evaluate the model accuracy on different circuits. Across all bit positions, voltage levels, and circuits, the model achieves on average a relative error of 1.06%. The model also achieves an average per-voltage Root Mean Square Error (RMSE) of 0.92% and per-bit RMSE of 1.02%. Exposing this error rate even up to the application level, the model can estimate the quality of an image processing application under voltage scaling with an average accuracy of 97.5%.