Innovative method for better utilization of emulation hardware /FPGA resources

Abstract

With shrinking time to market for VLSI industry, there is a constant need for hardware - software codevelopment in the VLSI design flow. FPGAs and Emulation systems offer a great help to verification and validation engineers to achieve the same in the VLSI design flow. Further, to enable design verification engineers to create close to real chip scenarios and interface with external peripherals like UART, JTAG, protocol and memory solutions further increases the need for FPGA or Emulation builds earlier in the design cycle. For accelerating smaller designs like IPs, FPGAs could suffice but for running complex SoCs, multi device FPGA architectures or Emulation systems might be needed. However, these acceleration hardware resources are expensive and it is important to make efficient use of them. This invention proposes a methodology for better area utilization of emulation/FPGA resources for a verification scenario/test by creating multiple instances of the design in a single test bench environment. We are able to see 2x-6x improvement in area and verification runtime by using this methodology depending on the type of design and its size.