Novel Step-Ramp Signal for Testing ADCS and DACS

Abstract

This paper presents a novel step-ramp signal (SRS) for testing analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A regulated clock signal (RCS) comes from regulating the frequency, duty cycle and amplitude of the system clock pulse which also serves as a trig pulse of a reference counter. The RCS is integrated by an Integrator to transform into the SRS which can accurately correspond with the output codes of the reference counter. With gradually increasing duty cycles according to the voltages of the SRS, the larger duty cycle the longer integration time is set up. Larger voltages from the integration of prolonged duty cycles are generated to compensate linkage currents at the capacitor. The problem of higher voltages resulting higher leakage currents at the capacitor in the Integrator can be overcome. The simulation results show that the accuracies of all ramp pieces of the SRS are within plusmn1/2LSB. The main advantages of the SRS for testing converters include accurate correspondence between the SRS and the reference counter and digital designs in linkage current compensation and in test response analyzers.