Trap-Assisted Passing Word Line Leakage and Variable Retention Time in DRAM

Abstract

As DRAM chips are scaling down, the reduction of retention time and reliability issue are getting more and more crucial. Through 3D TCAD simulations, the trap location and type effects on the access transistor leakage and reliability have been studied. The results indicate that different trap locations can induce opposite passing gate effects, and the GOX/Si interface traps are more important than STI/Si interface traps for suppressing the passing world line effects. Besides, the STI/Si interface traps will result in a coupling between passing word line effects and variable retention time(VRT) failure, which will make it difficult to capture and repair the VRT fail bits. Finally, some test methods have been suggested to capture more VRT cell to improve yield. This study has illustrated the correlation between the trap position and different failure model. It will guide manufactures to check the STI or gate oxide process according to the issues they faced.