Closed-loop MEMS accelerometer: From design to production

B. Grinberg, A. Feingold, L. Koenigsberg, L. Furman
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引用次数: 5

Abstract

The paper reports on a navigation grade 30g MEMS accelerometer based on digital ΔΣ modulation and capacitive sensing. The closed-loop accelerometer is a fully integrated system comprising a uniquely designed MEMS device enclosed in a specially built LCC package with a proprietary ASIC. Like Physical Logic's high-end open-loop MEMS accelerometers, now known as the MAXL-OL-2000 series, the closed-loop design benefits from the in-plane architecture using SOI wafer. Key features of the design are discussed, from the MEMS transducer to system wide considerations of low noise, high linearity, and robust stability of the control design. System level simulation results are presented and compared to the test results from the most recently fabricated MAXL-CL-3030 closed-loop ΔΣ accelerometer with 30g range. Physical Logic has developed a closed-loop MEMS accelerometer with an objective to reach inertial navigation grade performance. Both the high-end open-loop and closed-loop MEMS accelerometers employ a similar transducer design. In a different manner from the commonly used out-of-plane technique for bulk micromachining, an in-plane design using SOI wafer was adopted. The advantages of the approach are full bridge capacitive sensing for parasitic rejection, a highly symmetric mechanical structure for better temperature stability and elimination of the need for vacuum packaging for better reliability. A large proof mass, which is realized in SOI wafer handle layer, contributes to enhanced sensitivity. The closed-loop system architecture operates as a 4th order fabricated MAXL-CL-3030 closed-loop modulator used to convert external acceleration into a high frequency single bit digital signal. The design challenges and considerations are described with emphasis on noise, linearity, and stability. The test results of the MAXL-CL-3030 closed-loop ΔΣ accelerometer confirm the navigation grade design. Measurements are presented demonstrating results of <;20 μg bias stability, 0.01 % typical non-linearity, and less than 10 μg/g2rms Vibration Rectification Error (VRE) up to a 2 kHz frequency range.
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闭环MEMS加速度计:从设计到生产
本文报道了一种基于数字ΔΣ调制和电容传感的导航级30g MEMS加速度计。闭环加速度计是一个完全集成的系统,包括一个独特设计的MEMS器件,封装在带有专用ASIC的特制LCC封装中。与Physical Logic的高端开环MEMS加速度计(现在称为MAXL-OL-2000系列)一样,闭环设计得益于使用SOI晶圆的平面内架构。讨论了该设计的主要特点,从MEMS传感器到系统范围内的低噪声、高线性度和鲁棒稳定性的控制设计。给出了系统级仿真结果,并与最近制造的MAXL-CL-3030闭环加速度计ΔΣ的测试结果进行了比较,其量程为30g。物理逻辑公司开发了一种闭环MEMS加速度计,目标是达到惯性导航级的性能。高端开环和闭环MEMS加速度计都采用类似的传感器设计。不同于本体微加工常用的面外技术,采用了SOI晶圆的面内设计。该方法的优点是全桥电容感测可抑制寄生,高度对称的机械结构可获得更好的温度稳定性,并且无需真空封装以获得更好的可靠性。在SOI晶圆柄层中实现了较大的验证质量,有助于提高灵敏度。闭环系统架构作为四阶制造的MAXL-CL-3030闭环调制器,用于将外部加速度转换为高频单比特数字信号。设计挑战和注意事项的描述,重点是噪声,线性和稳定性。MAXL-CL-3030闭环ΔΣ加速度计的测试结果证实了导航级设计。测量结果表明,在2khz频率范围内,偏置稳定性< 0.20 μg,典型非线性0.01%,振动纠偏误差(VRE)小于10 μg/g2rms。
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